In integrated circuit (IC) chips, patterns of metal are used to electrically interconnect the electronic components making up the integrated circuit. Proper interconnection of the various electronic components is essential to proper and reliable performance. Thus, the occurrence of short or open circuits or other defects in the interconnect structure(s) is problematic for overall reliability. Interconnect problems may be caused not only by defects in the interconnect structures themselves, but also by defects in the portions of the chip in the vicinity of the interconnect structure. Such defects may manifest themselves during subsequent manufacturing steps leading to chip rejection or during actual use leading to problems for the end user of the IC-containing device.
Typically, interconnects are formed by depositing a layer of the desired electrically conductive material (typically, a metal or alloy) on a semiconductor substrate (i.e. over whatever other layers may already present on the substrate). Auxiliary conductive layers (e.g. Ti or TiN) may be deposited before and/or after deposition of the electrically conductive metal layer such that the auxiliary layers lie directly above and/or below the electrically conductive metal layer. The auxiliary layers are generally used to enhance the device reliability and to act as barrier layers between interconnect metallurgy and other portions of the overall IC structure (e.g., underlying or overlying dielectric layers, etc.). Portions of the conductive material layer(s) (including any auxiliary layers present) are then removed selectively whereby the conductive material remaining on the substrate forms a pattern corresponding to the desired interconnect structure.
Formation of the desired interconnect structure from the deposited conductive layer(s) is usually achieved by applying a photoresist layer over the unpatterned conductive layer(s) (i.e. over the uppermost conductive layer). The photoresist is then pattern-wise exposed to radiation and developed (i.e. portions of the photoresist layer are removed) to reveal a photoresist pattern corresponding to the pattern of the desired interconnect structure. The conductive layer(s) is then typically etched to remove the portions of the conductive layer not covered by the photoresist pattern. When the desired removal is completed, the remaining photoresist is removed to reveal the conductive material pattern (i.e. the desired interconnect structure) on the substrate. Typically, the conductive material pattern (e.g. one or more lines) has vertical or sloped sidewalls such that the pattern at the underlying substrate surface is equal or greater ir area than the pattern at the top surface of the conductive material furthest from the underlying substrate surface.
Once the desired interconnect structure is formed, typically a dielectric layer is deposited over and between the features of the interconnect structure to protect and appropriately isolate the interconnect structure.
While the above process is generally known, defects (such as voids in the interconnect metallurgy or in the dielectric deposited adjacent to the interconnect structure) can be generated by the process. Defects can be tolerated to some extent, but defects become less tolerable with reduced feature dimensions and more complex designs associated with integrated circuit manufacture. Thus, there is a need for improved interconnect structure formation processes which reduce or eliminate the occurrence of defects.